KRSをKria KV260上で動かしてみる の続き。 simple_adder を例に、合成レポートなどを確認してみた。 詳細な性能の確認などはここでは行わず、正常にレポートの結果が得られるのかを確認することを目的とする。
動作環境
- OS : Ubuntu 20.04.3 LTS（64 bit）
- Vivado : 2022.1
- Vitis : 2022.1
- Vitis_HLS : 2022.1
- ROS2 : Humble
- ボード : Kria KV260
高位合成の実行
以下のコマンドを実行し、高位合成を行う。
$ colcon acceleration hls --run simple_adder
Found Tcl script "project_simpleadder1.tcl" for package: simple_adder
Executing /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder1.tcl
Found Tcl script "project_simpleadder2.tcl" for package: simple_adder
Executing /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder2.tcl
Project: project_simpleadder1
Path: /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder1
- Solution: solution_4ns
- C Simulation: Pass
- C Synthesis: Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Run
- System Generator: Not Run
- Export Evaluation: Not Run
Project: project_simpleadder2
Path: /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder2
- Solution: solution_4ns
- C Simulation: Pass
- C Synthesis: Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Run
- System Generator: Not Run
- Export Evaluation: Not Run
- Solution: solution_10ns
- C Simulation: Pass
- C Synthesis: Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Run
- System Generator: Not Run
- Export Evaluation: Not Run
サマリーの確認
以下のコマンドを実行し、高位合成のレポートのサマリーを確認する。
$ colcon acceleration hls --summary simple_adder
# /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder1.tcl
Solution# tar.clk est.clk latency_max BRAM_18K DSP FF LUT
solution_4ns 4.00 2.016 0 0 (0%) 0 (0%) 181 (~0%) 291 (~0%)
# /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder2.tcl
Solution# tar.clk est.clk latency_max BRAM_18K DSP FF LUT
solution_10ns 10.00 5.436 10.000 0 (0%) 9 (~0%) 214 (~0%) 365 (~0%)
solution_4ns 4.00 2.365 20.000 0 (0%) 9 (~0%) 745 (~0%) 466 (~0%)
高位合成レポートの確認
以下のコマンドを実行し、高位合成のレポートを確認する。
$ colcon acceleration hls --run --synthesis-report simple_adder
Found Tcl script "project_simpleadder1.tcl" for package: simple_adder
Executing /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder1.tcl
Found Tcl script "project_simpleadder2.tcl" for package: simple_adder
Executing /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder2.tcl
Project: project_simpleadder1
Path: /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder1
- Solution: solution_4ns
- C Simulation: Pass
- C Synthesis: Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Run
- System Generator: Not Run
- Export Evaluation: Not Run
- Synthesis report: /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder1/solution_4ns/syn/report/simple_adder_csynth.rpt
================================================================
== Vitis HLS Report for 'simple_adder'
================================================================
* Date: Sun Sep 11 08:36:36 2022
* Version: 2022.1.2 (Build 3605665 on Fri Aug 5 22:52:02 MDT 2022)
* Project: project_simpleadder1
* Solution: solution_4ns (Vitis Kernel Flow Target)
* Product family: zynquplus
* Target device: xck26-sfvc784-2LV-c
================================================================
== Performance Estimates
================================================================
+ Timing:
* Summary:
+--------+---------+----------+------------+
| Clock | Target | Estimated| Uncertainty|
+--------+---------+----------+------------+
|ap_clk | 4.00 ns| 2.016 ns| 1.08 ns|
+--------+---------+----------+------------+
+ Latency:
* Summary:
+---------+---------+----------+----------+-----+-----+---------+
| Latency (cycles) | Latency (absolute) | Interval | Pipeline|
| min | max | min | max | min | max | Type |
+---------+---------+----------+----------+-----+-----+---------+
| 0| 0| 0 ns| 0 ns| 1| 1| no|
+---------+---------+----------+----------+-----+-----+---------+
+ Detail:
* Instance:
N/A
* Loop:
N/A
================================================================
== Utilization Estimates
================================================================
* Summary:
+-----------------+---------+------+--------+--------+-----+
| Name | BRAM_18K| DSP | FF | LUT | URAM|
+-----------------+---------+------+--------+--------+-----+
|DSP | -| -| -| -| -|
|Expression | -| -| 0| 41| -|
|FIFO | -| -| -| -| -|
|Instance | 0| -| 144| 232| 0|
|Memory | -| -| -| -| -|
|Multiplexer | -| -| -| 18| -|
|Register | -| -| 37| -| -|
+-----------------+---------+------+--------+--------+-----+
|Total | 0| 0| 181| 291| 0|
+-----------------+---------+------+--------+--------+-----+
|Available | 288| 1248| 234240| 117120| 64|
+-----------------+---------+------+--------+--------+-----+
|Utilization (%) | 0| 0| ~0| ~0| 0|
+-----------------+---------+------+--------+--------+-----+
+ Detail:
* Instance:
+-----------------+---------------+---------+----+-----+-----+-----+
| Instance | Module | BRAM_18K| DSP| FF | LUT | URAM|
+-----------------+---------------+---------+----+-----+-----+-----+
|control_s_axi_U |control_s_axi | 0| 0| 144| 232| 0|
+-----------------+---------------+---------+----+-----+-----+-----+
|Total | | 0| 0| 144| 232| 0|
+-----------------+---------------+---------+----+-----+-----+-----+
* DSP:
N/A
* Memory:
N/A
* FIFO:
N/A
* Expression:
+-----------------+----------+----+---+----+------------+------------+
| Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1|
+-----------------+----------+----+---+----+------------+------------+
|c_fu_46_p2 | +| 0| 0| 39| 32| 32|
|ap_block_state1 | or| 0| 0| 2| 1| 1|
+-----------------+----------+----+---+----+------------+------------+
|Total | | 0| 0| 41| 33| 33|
+-----------------+----------+----+---+----+------------+------------+
* Multiplexer:
+-----------+----+-----------+-----+-----------+
| Name | LUT| Input Size| Bits| Total Bits|
+-----------+----+-----------+-----+-----------+
|ap_done | 9| 2| 1| 2|
|ap_return | 9| 2| 32| 64|
+-----------+----+-----------+-----+-----------+
|Total | 18| 4| 33| 66|
+-----------+----+-----------+-----+-----------+
* Register:
+----------------+----+----+-----+-----------+
| Name | FF | LUT| Bits| Const Bits|
+----------------+----+----+-----+-----------+
|ap_CS_fsm | 1| 0| 1| 0|
|ap_done_reg | 1| 0| 1| 0|
|ap_return_preg | 32| 0| 32| 0|
|ap_rst_n_inv | 1| 0| 1| 0|
|ap_rst_reg_1 | 1| 0| 1| 0|
|ap_rst_reg_2 | 1| 0| 1| 0|
+----------------+----+----+-----+-----------+
|Total | 37| 0| 37| 0|
+----------------+----+----+-----+-----------+
================================================================
== Interface
================================================================
* Summary:
+-----------------------+-----+-----+---------------+--------------+--------------+
| RTL Ports | Dir | Bits| Protocol | Source Object| C Type |
+-----------------------+-----+-----+---------------+--------------+--------------+
|s_axi_control_AWVALID | in| 1| s_axi| control| scalar|
|s_axi_control_AWREADY | out| 1| s_axi| control| scalar|
|s_axi_control_AWADDR | in| 6| s_axi| control| scalar|
|s_axi_control_WVALID | in| 1| s_axi| control| scalar|
|s_axi_control_WREADY | out| 1| s_axi| control| scalar|
|s_axi_control_WDATA | in| 32| s_axi| control| scalar|
|s_axi_control_WSTRB | in| 4| s_axi| control| scalar|
|s_axi_control_ARVALID | in| 1| s_axi| control| scalar|
|s_axi_control_ARREADY | out| 1| s_axi| control| scalar|
|s_axi_control_ARADDR | in| 6| s_axi| control| scalar|
|s_axi_control_RVALID | out| 1| s_axi| control| scalar|
|s_axi_control_RREADY | in| 1| s_axi| control| scalar|
|s_axi_control_RDATA | out| 32| s_axi| control| scalar|
|s_axi_control_RRESP | out| 2| s_axi| control| scalar|
|s_axi_control_BVALID | out| 1| s_axi| control| scalar|
|s_axi_control_BREADY | in| 1| s_axi| control| scalar|
|s_axi_control_BRESP | out| 2| s_axi| control| scalar|
|ap_clk | in| 1| ap_ctrl_chain| simple_adder| return value|
|ap_rst_n | in| 1| ap_ctrl_chain| simple_adder| return value|
|interrupt | out| 1| ap_ctrl_chain| simple_adder| return value|
+-----------------------+-----+-----+---------------+--------------+--------------+
Project: project_simpleadder2
Path: /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder2
- Solution: solution_4ns
- C Simulation: Pass
- C Synthesis: Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Run
- System Generator: Not Run
- Export Evaluation: Not Run
- Synthesis report: /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder2/solution_4ns/syn/report/simple_adder_csynth.rpt
================================================================
== Vitis HLS Report for 'simple_adder'
================================================================
* Date: Sun Sep 11 08:36:55 2022
* Version: 2022.1.2 (Build 3605665 on Fri Aug 5 22:52:02 MDT 2022)
* Project: project_simpleadder2
* Solution: solution_4ns (Vitis Kernel Flow Target)
* Product family: zynquplus
* Target device: xck26-sfvc784-2LV-c
================================================================
== Performance Estimates
================================================================
+ Timing:
* Summary:
+--------+---------+----------+------------+
| Clock | Target | Estimated| Uncertainty|
+--------+---------+----------+------------+
|ap_clk | 4.00 ns| 2.365 ns| 1.08 ns|
+--------+---------+----------+------------+
+ Latency:
* Summary:
+---------+---------+-----------+-----------+-----+-----+---------+
| Latency (cycles) | Latency (absolute) | Interval | Pipeline|
| min | max | min | max | min | max | Type |
+---------+---------+-----------+-----------+-----+-----+---------+
| 5| 5| 20.000 ns| 20.000 ns| 6| 6| no|
+---------+---------+-----------+-----------+-----+-----+---------+
+ Detail:
* Instance:
N/A
* Loop:
N/A
================================================================
== Utilization Estimates
================================================================
* Summary:
+-----------------+---------+------+--------+--------+-----+
| Name | BRAM_18K| DSP | FF | LUT | URAM|
+-----------------+---------+------+--------+--------+-----+
|DSP | -| -| -| -| -|
|Expression | -| -| 0| 41| -|
|FIFO | -| -| -| -| -|
|Instance | 0| 9| 639| 379| 0|
|Memory | -| -| -| -| -|
|Multiplexer | -| -| -| 46| -|
|Register | -| -| 106| -| -|
+-----------------+---------+------+--------+--------+-----+
|Total | 0| 9| 745| 466| 0|
+-----------------+---------+------+--------+--------+-----+
|Available | 288| 1248| 234240| 117120| 64|
+-----------------+---------+------+--------+--------+-----+
|Utilization (%) | 0| ~0| ~0| ~0| 0|
+-----------------+---------+------+--------+--------+-----+
+ Detail:
* Instance:
+-----------------------+--------------------+---------+----+-----+-----+-----+
| Instance | Module | BRAM_18K| DSP| FF | LUT | URAM|
+-----------------------+--------------------+---------+----+-----+-----+-----+
|control_s_axi_U |control_s_axi | 0| 0| 144| 232| 0|
|mul_32s_32s_32_2_1_U1 |mul_32s_32s_32_2_1 | 0| 3| 165| 49| 0|
|mul_32s_32s_32_2_1_U2 |mul_32s_32s_32_2_1 | 0| 3| 165| 49| 0|
|mul_32s_32s_32_2_1_U3 |mul_32s_32s_32_2_1 | 0| 3| 165| 49| 0|
+-----------------------+--------------------+---------+----+-----+-----+-----+
|Total | | 0| 9| 639| 379| 0|
+-----------------------+--------------------+---------+----+-----+-----+-----+
* DSP:
N/A
* Memory:
N/A
* FIFO:
N/A
* Expression:
+-----------------+----------+----+---+----+------------+------------+
| Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1|
+-----------------+----------+----+---+----+------------+------------+
|ap_return | +| 0| 0| 39| 32| 32|
|ap_block_state1 | or| 0| 0| 2| 1| 1|
+-----------------+----------+----+---+----+------------+------------+
|Total | | 0| 0| 41| 33| 33|
+-----------------+----------+----+---+----+------------+------------+
* Multiplexer:
+-----------+----+-----------+-----+-----------+
| Name | LUT| Input Size| Bits| Total Bits|
+-----------+----+-----------+-----+-----------+
|ap_NS_fsm | 37| 7| 1| 7|
|ap_done | 9| 2| 1| 2|
+-----------+----+-----------+-----+-----------+
|Total | 46| 9| 2| 9|
+-----------+----+-----------+-----+-----------+
* Register:
+-------------------+----+----+-----+-----------+
| Name | FF | LUT| Bits| Const Bits|
+-------------------+----+----+-----+-----------+
|ap_CS_fsm | 6| 0| 6| 0|
|ap_done_reg | 1| 0| 1| 0|
|ap_rst_n_inv | 1| 0| 1| 0|
|ap_rst_reg_1 | 1| 0| 1| 0|
|ap_rst_reg_2 | 1| 0| 1| 0|
|mul_ln20_1_reg_80 | 32| 0| 32| 0|
|mul_ln20_2_reg_85 | 32| 0| 32| 0|
|mul_ln20_reg_75 | 32| 0| 32| 0|
+-------------------+----+----+-----+-----------+
|Total | 106| 0| 106| 0|
+-------------------+----+----+-----+-----------+
================================================================
== Interface
================================================================
* Summary:
+-----------------------+-----+-----+---------------+--------------+--------------+
| RTL Ports | Dir | Bits| Protocol | Source Object| C Type |
+-----------------------+-----+-----+---------------+--------------+--------------+
|s_axi_control_AWVALID | in| 1| s_axi| control| scalar|
|s_axi_control_AWREADY | out| 1| s_axi| control| scalar|
|s_axi_control_AWADDR | in| 6| s_axi| control| scalar|
|s_axi_control_WVALID | in| 1| s_axi| control| scalar|
|s_axi_control_WREADY | out| 1| s_axi| control| scalar|
|s_axi_control_WDATA | in| 32| s_axi| control| scalar|
|s_axi_control_WSTRB | in| 4| s_axi| control| scalar|
|s_axi_control_ARVALID | in| 1| s_axi| control| scalar|
|s_axi_control_ARREADY | out| 1| s_axi| control| scalar|
|s_axi_control_ARADDR | in| 6| s_axi| control| scalar|
|s_axi_control_RVALID | out| 1| s_axi| control| scalar|
|s_axi_control_RREADY | in| 1| s_axi| control| scalar|
|s_axi_control_RDATA | out| 32| s_axi| control| scalar|
|s_axi_control_RRESP | out| 2| s_axi| control| scalar|
|s_axi_control_BVALID | out| 1| s_axi| control| scalar|
|s_axi_control_BREADY | in| 1| s_axi| control| scalar|
|s_axi_control_BRESP | out| 2| s_axi| control| scalar|
|ap_clk | in| 1| ap_ctrl_chain| simple_adder| return value|
|ap_rst_n | in| 1| ap_ctrl_chain| simple_adder| return value|
|interrupt | out| 1| ap_ctrl_chain| simple_adder| return value|
+-----------------------+-----+-----+---------------+--------------+--------------+
- Solution: solution_10ns
- C Simulation: Pass
- C Synthesis: Run
- C/RTL Co-simulation: Not Run
- Export:
- IP Catalog: Run
- System Generator: Not Run
- Export Evaluation: Not Run
- Synthesis report: /home/np/krs_ws/build-kv260/simple_adder/project_simpleadder2/solution_10ns/syn/report/simple_adder_csynth.rpt
================================================================
== Vitis HLS Report for 'simple_adder'
================================================================
* Date: Sun Sep 11 08:37:11 2022
* Version: 2022.1.2 (Build 3605665 on Fri Aug 5 22:52:02 MDT 2022)
* Project: project_simpleadder2
* Solution: solution_10ns (Vitis Kernel Flow Target)
* Product family: zynquplus
* Target device: xck26-sfvc784-2LV-c
================================================================
== Performance Estimates
================================================================
+ Timing:
* Summary:
+--------+----------+----------+------------+
| Clock | Target | Estimated| Uncertainty|
+--------+----------+----------+------------+
|ap_clk | 10.00 ns| 5.436 ns| 2.70 ns|
+--------+----------+----------+------------+
+ Latency:
* Summary:
+---------+---------+-----------+-----------+-----+-----+---------+
| Latency (cycles) | Latency (absolute) | Interval | Pipeline|
| min | max | min | max | min | max | Type |
+---------+---------+-----------+-----------+-----+-----+---------+
| 1| 1| 10.000 ns| 10.000 ns| 2| 2| no|
+---------+---------+-----------+-----------+-----+-----+---------+
+ Detail:
* Instance:
N/A
* Loop:
N/A
================================================================
== Utilization Estimates
================================================================
* Summary:
+-----------------+---------+------+--------+--------+-----+
| Name | BRAM_18K| DSP | FF | LUT | URAM|
+-----------------+---------+------+--------+--------+-----+
|DSP | -| -| -| -| -|
|Expression | -| -| 0| 41| -|
|FIFO | -| -| -| -| -|
|Instance | 0| 9| 144| 292| 0|
|Memory | -| -| -| -| -|
|Multiplexer | -| -| -| 32| -|
|Register | -| -| 70| -| -|
+-----------------+---------+------+--------+--------+-----+
|Total | 0| 9| 214| 365| 0|
+-----------------+---------+------+--------+--------+-----+
|Available | 288| 1248| 234240| 117120| 64|
+-----------------+---------+------+--------+--------+-----+
|Utilization (%) | 0| ~0| ~0| ~0| 0|
+-----------------+---------+------+--------+--------+-----+
+ Detail:
* Instance:
+-----------------------+--------------------+---------+----+-----+-----+-----+
| Instance | Module | BRAM_18K| DSP| FF | LUT | URAM|
+-----------------------+--------------------+---------+----+-----+-----+-----+
|control_s_axi_U |control_s_axi | 0| 0| 144| 232| 0|
|mul_32s_32s_32_1_1_U1 |mul_32s_32s_32_1_1 | 0| 3| 0| 20| 0|
|mul_32s_32s_32_1_1_U2 |mul_32s_32s_32_1_1 | 0| 3| 0| 20| 0|
|mul_32s_32s_32_1_1_U3 |mul_32s_32s_32_1_1 | 0| 3| 0| 20| 0|
+-----------------------+--------------------+---------+----+-----+-----+-----+
|Total | | 0| 9| 144| 292| 0|
+-----------------------+--------------------+---------+----+-----+-----+-----+
* DSP:
N/A
* Memory:
N/A
* FIFO:
N/A
* Expression:
+-----------------+----------+----+---+----+------------+------------+
| Variable Name | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1|
+-----------------+----------+----+---+----+------------+------------+
|c_fu_62_p2 | +| 0| 0| 39| 32| 32|
|ap_block_state1 | or| 0| 0| 2| 1| 1|
+-----------------+----------+----+---+----+------------+------------+
|Total | | 0| 0| 41| 33| 33|
+-----------------+----------+----+---+----+------------+------------+
* Multiplexer:
+-----------+----+-----------+-----+-----------+
| Name | LUT| Input Size| Bits| Total Bits|
+-----------+----+-----------+-----+-----------+
|ap_NS_fsm | 14| 3| 1| 3|
|ap_done | 9| 2| 1| 2|
|ap_return | 9| 2| 32| 64|
+-----------+----+-----------+-----+-----------+
|Total | 32| 7| 34| 69|
+-----------+----+-----------+-----+-----------+
* Register:
+-----------------+----+----+-----+-----------+
| Name | FF | LUT| Bits| Const Bits|
+-----------------+----+----+-----+-----------+
|ap_CS_fsm | 2| 0| 2| 0|
|ap_done_reg | 1| 0| 1| 0|
|ap_return_preg | 32| 0| 32| 0|
|ap_rst_n_inv | 1| 0| 1| 0|
|ap_rst_reg_1 | 1| 0| 1| 0|
|ap_rst_reg_2 | 1| 0| 1| 0|
|mul_ln20_reg_73 | 32| 0| 32| 0|
+-----------------+----+----+-----+-----------+
|Total | 70| 0| 70| 0|
+-----------------+----+----+-----+-----------+
================================================================
== Interface
================================================================
* Summary:
+-----------------------+-----+-----+---------------+--------------+--------------+
| RTL Ports | Dir | Bits| Protocol | Source Object| C Type |
+-----------------------+-----+-----+---------------+--------------+--------------+
|s_axi_control_AWVALID | in| 1| s_axi| control| scalar|
|s_axi_control_AWREADY | out| 1| s_axi| control| scalar|
|s_axi_control_AWADDR | in| 6| s_axi| control| scalar|
|s_axi_control_WVALID | in| 1| s_axi| control| scalar|
|s_axi_control_WREADY | out| 1| s_axi| control| scalar|
|s_axi_control_WDATA | in| 32| s_axi| control| scalar|
|s_axi_control_WSTRB | in| 4| s_axi| control| scalar|
|s_axi_control_ARVALID | in| 1| s_axi| control| scalar|
|s_axi_control_ARREADY | out| 1| s_axi| control| scalar|
|s_axi_control_ARADDR | in| 6| s_axi| control| scalar|
|s_axi_control_RVALID | out| 1| s_axi| control| scalar|
|s_axi_control_RREADY | in| 1| s_axi| control| scalar|
|s_axi_control_RDATA | out| 32| s_axi| control| scalar|
|s_axi_control_RRESP | out| 2| s_axi| control| scalar|
|s_axi_control_BVALID | out| 1| s_axi| control| scalar|
|s_axi_control_BREADY | in| 1| s_axi| control| scalar|
|s_axi_control_BRESP | out| 2| s_axi| control| scalar|
|ap_clk | in| 1| ap_ctrl_chain| simple_adder| return value|
|ap_rst_n | in| 1| ap_ctrl_chain| simple_adder| return value|
|interrupt | out| 1| ap_ctrl_chain| simple_adder| return value|
+-----------------------+-----+-----+---------------+--------------+--------------+